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- 查询最新版本概念体系节点树GET
- 查询包含合并状态信息概念体系节点树GET
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- 查询概念体系节点列表【内部】GET
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- 测试接口 CopyGET
- 官网
查询包含合并状态信息概念体系节点树
开发中
GET
/api/concept/node/mergedStatusTree
请求参数
Query 参数
knowledgeId
string
必需
示例值:
69
version
number
必需
示例值:
0.5
Header 参数
Authorization
string
必需
默认值:
{{jwtToken}}
示例代码
Shell
JavaScript
Java
Swift
Go
PHP
Python
HTTP
C
C#
Objective-C
Ruby
OCaml
Dart
R
请求示例请求示例
Shell
JavaScript
Java
Swift
curl --location --request GET 'http://develop.tianxin.supermind.quant-chi.com:8045/api/concept/node/mergedStatusTree?knowledgeId=69&version=0.5' \
--header 'Authorization;'返回响应
🟢200成功
application/json
Body
body
object
必需
nodeId
string
必需
parentId
string
必需
nodeCount
null
必需
name
string
必需
englishName
string
必需
knowledgeLabel
null
必需
description
string
必需
desc
null
必需
alterName
null
必需
chineseSemanticRule
null
必需
englisSemanticRule
null
必需
englishSemanticRule
null
必需
keywordExclude
null
必需
knowledgeBottleneck
null
必需
teckParam
null
必需
version
number
版本
isHooked
integer
必需
mergedStatus
integer
必需
children
array [object {20}]
必需
isRiskNode
integer
必需
riskLevel
null
必需
header
object
必需
code
integer
必需
message
string
必需
示例
{
"body": {
"nodeId": "697443b83a91b861e14dae217a01ec4d",
"parentId": "root",
"nodeCount": null,
"name": "集成电路",
"englishName": "",
"knowledgeLabel": null,
"description": "集成电路（integrated circuit）是一种微型电子器件或部件。采用一定的工艺，把一个电路中所需的晶体管、电阻、电容和电感等元件及布线互连一起，制作在一小块或几小块半导体晶片或介质基片上，然后封装在一个管壳内，成为具有所需电路功能的微型结构；其中所有元件在结构上已组成一个整体，使电子元件向着微小型化、低功耗、智能化和高可靠性方面迈进了一大步。它在电路中用字母“IC”表示。",
"level": 0,
"desc": null,
"alterName": null,
"chineseSemanticRule": null,
"englisSemanticRule": null,
"englishSemanticRule": null,
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "abe53b2a4fa2695c286beb5f46f6cdf3",
"parentId": "697443b83a91b861e14dae217a01ec4d",
"nodeCount": null,
"name": "中游",
"englishName": "",
"knowledgeLabel": null,
"description": "",
"level": 1,
"desc": null,
"alterName": null,
"chineseSemanticRule": null,
"englisSemanticRule": null,
"englishSemanticRule": null,
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "9b13a28e461b0caa682176d505c560b3",
"parentId": "abe53b2a4fa2695c286beb5f46f6cdf3",
"nodeCount": null,
"name": "集成电路制造",
"englishName": "",
"knowledgeLabel": null,
"description": "集成电路制造是指集成电路制造过程中由单台设备或单个反应腔室（Chamber）即可完成的工艺步骤",
"level": 2,
"desc": null,
"alterName": null,
"chineseSemanticRule": null,
"englisSemanticRule": null,
"englishSemanticRule": null,
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "00683859edc5806baf892e045ff76235",
"parentId": "9b13a28e461b0caa682176d505c560b3",
"nodeCount": null,
"name": "集成电路晶圆代工",
"englishName": "",
"knowledgeLabel": null,
"description": "晶圆代工就是向专业的集成电路设计公司或电子厂商提供专门的制造服务。",
"level": 3,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"晶圆|代工",
"硅晶|代工",
"晶圆|生产",
"硅晶|生产"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Wafer|Foundry",
"Silicon|Foundry",
"Wafer|Production",
"Silicon|Production"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "5969986c3af7cf6906975382ee048745",
"parentId": "9b13a28e461b0caa682176d505c560b3",
"nodeCount": null,
"name": "垂直整合制造（IDM）",
"englishName": "",
"knowledgeLabel": null,
"description": "IDM (Integrated Device Manufacture)即垂直整合制造模式，IDM企业集芯片设计、芯片制造、芯片封装和测试等多个产业链环节于一身，仅有极少数企业能够维持这种模式。",
"level": 3,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"垂直整合|制造"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Vertical Integration|Manufacturing"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
}
],
"isRiskNode": 0,
"riskLevel": null
}
],
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "be01e5e0031e92c29f743dc0f4c36ee0",
"parentId": "697443b83a91b861e14dae217a01ec4d",
"nodeCount": null,
"name": "下游",
"englishName": "",
"knowledgeLabel": null,
"description": "",
"level": 1,
"desc": null,
"alterName": null,
"chineseSemanticRule": null,
"englisSemanticRule": null,
"englishSemanticRule": null,
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "6ee7f79882644a6616053477d308e356",
"parentId": "be01e5e0031e92c29f743dc0f4c36ee0",
"nodeCount": null,
"name": "集成电路封装测试",
"englishName": "",
"knowledgeLabel": null,
"description": "集成电路封装测试在电子学金字塔中的位置既是金字塔的尖顶又是金字塔的基座。说它同时处在这两种位置都有很充分的根据。从电子元器件（如晶体管）的密度这个角度上来说，IC代表了电子学的尖端。但是IC又是一个起始点，是一种基本结构单元，是组成我们生活中大多数电子系统的基础。同样，IC不仅仅是单块芯片或者基本电子结构，IC的种类千差万别（模拟电路、数字电路、射频电路、传感器等），因而对于封装的需求和要求也各不相同。本文对IC封装技术做了全面的回顾，以粗线条的方式介绍了制造这些不可缺少的封装结构时用到的各种材料和工艺。",
"level": 2,
"desc": null,
"alterName": null,
"chineseSemanticRule": null,
"englisSemanticRule": null,
"englishSemanticRule": null,
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "c93ce57c9960cb378bcbfff1c1f1ae41",
"parentId": "6ee7f79882644a6616053477d308e356",
"nodeCount": null,
"name": "集成电路封装",
"englishName": "",
"knowledgeLabel": null,
"description": "集成电路封装在电子学金字塔中的位置既是金字塔的尖顶又是金字塔的基座。说它同时处在这两种位置都有很充分的根据。从电子元器件（如晶体管）的密度这个角度上来说，IC代表了电子学的尖端。但是IC又是一个起始点，是一种基本结构单元，是组成我们生活中大多数电子系统的基础。同样，IC不仅仅是单块芯片或者基本电子结构，IC的种类千差万别（模拟电路、数字电路、射频电路、传感器等），因而对于封装的需求和要求也各不相同。本文对IC封装技术做了全面的回顾，以粗线条的方式介绍了制造这些不可缺少的封装结构时用到的各种材料和工艺。",
"level": 3,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"集成电路|封装",
"IC封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Integrated Circuits|Package",
"IC|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "85a5496beb1acb2b5350ca2e60946861",
"parentId": "c93ce57c9960cb378bcbfff1c1f1ae41",
"nodeCount": null,
"name": "先进芯片封装",
"englishName": "",
"knowledgeLabel": null,
"description": "包括倒装（FlipChip），凸块（Bumping），晶圆级封装（Waferlevelpackage），2.5D封装（interposer，RDL等），3D封装（TSV）等封装技术",
"level": 4,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"先进|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Advanced|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "9f7558d49c82b9c2283031b1d6707587",
"parentId": "85a5496beb1acb2b5350ca2e60946861",
"nodeCount": null,
"name": "FC封装",
"englishName": "",
"knowledgeLabel": null,
"description": "FC封装是反转芯片，这种封装中有针脚插入插座。这些芯片被反转，以至片模或构成计算机芯片的处理器部分被暴露在处理器的上部。",
"level": 5,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"FC|封装",
"倒装芯片|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"FC|Package",
"Flip Chip|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "625d3cbe028e53186d38150988ed9c80",
"parentId": "85a5496beb1acb2b5350ca2e60946861",
"nodeCount": null,
"name": "WLP封装",
"englishName": "",
"knowledgeLabel": null,
"description": "晶片级封装 (WLP)是芯片封装 (CSP)的一种，可以使IC面向下贴装到印刷电路板 (PCB)上，采用传统的SMT安装工艺。",
"level": 5,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"WLP|封装",
"晶圆|封装",
"晶片|封装",
"WLCSP|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"WLP|Package",
"Wafer|Package",
"Chip|Package",
"WLCSP|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "4ce64714c45f0c78f42f983698681c58",
"parentId": "625d3cbe028e53186d38150988ed9c80",
"nodeCount": null,
"name": "扇入型WLP封装",
"englishName": "",
"knowledgeLabel": null,
"description": "扇入型WLP封装原理就是在原芯片尺寸内部将所需要的I/O口排列完成，封装尺寸基本等于芯片尺寸的封装方式。",
"level": 6,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"扇入|WLP|封装",
"扇入|晶圆|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Fan In|WLP|Package",
"Fan In|Wafer|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "5f64aab28db846cd00d69bb6fbca7a1f",
"parentId": "625d3cbe028e53186d38150988ed9c80",
"nodeCount": null,
"name": "扇出型WLP封装",
"englishName": "",
"knowledgeLabel": null,
"description": "扇出型晶圆级封装的英文全称为（Fan-Out Wafer Level Packaging；FOWLP），其采取拉线出来的方式，扇出的原理就是在原芯片尺寸内部无法全部排布所需的I/O口数量时，通过特殊的填充材料，人为扩大芯片的封装尺寸，并在整个封装范围上走线和排布I/O。",
"level": 6,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"扇出|WLP|封装",
"扇出|晶圆|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Fanout|WLP|Package",
"Fanout|Wafer|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
}
],
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "705e340a8646213e17578f262e754041",
"parentId": "85a5496beb1acb2b5350ca2e60946861",
"nodeCount": null,
"name": "2.5D封装",
"englishName": "",
"knowledgeLabel": null,
"description": "2.5D封装是传统2D IC封装技术的进步，可实现更精细的线路与空间利用。通常用于高端ASIC、FPGA、GPU和内存立方体。",
"level": 5,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"2.5D|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"2.5D|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "acc98d20bbfb4d78c89df99088ee885a",
"parentId": "85a5496beb1acb2b5350ca2e60946861",
"nodeCount": null,
"name": "3D封装",
"englishName": "",
"knowledgeLabel": null,
"description": "3D晶圆级封装，英文简称（WLP)，包括CIS发射器、MEMS封装、标准器件封装。是指在不改变封装体尺寸的前提下，在同一个封装体内于垂直方向叠放两个以上芯片的封装技术，它起源于快闪存储器(NOR/NAND)及SDRAM的叠层封装。主要特点包括：多功能、高效能；大容量高密度，单位体积上的功能及应用成倍提升以及低成本。",
"level": 5,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"3D|封装",
"WLP|封装",
"叠层芯片|封装",
"立体|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"3D|Package",
"Wafer|Package",
"WLP|Package",
"Stacked Chip|Package",
"Stereo|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": null,
"isRiskNode": 0,
"riskLevel": null
}
],
"isRiskNode": 0,
"riskLevel": null
},
{
"nodeId": "2d8f3327fd91a62cf6f13591b6930633",
"parentId": "c93ce57c9960cb378bcbfff1c1f1ae41",
"nodeCount": null,
"name": "传统芯片封装",
"englishName": "",
"knowledgeLabel": null,
"description": "传统芯片封装是指将通过测试的晶圆按照产品型号及功能需求加工得到独立芯片的过程。封装过程为：来自晶圆前道工艺的晶圆通过划片工艺后被切割为小的晶片（Die），然后将切割好的晶片用胶水贴装到相应的基板（引线框架）架的小岛上，再利用超细的金属（金锡铜铝）导线或者导电性树脂将晶片的接合焊盘（BondPad）连接到基板的相应引脚（Lead）,并构成所要求的电路；然后再对独立的晶片用塑料外壳加以封装保护，塑封之后还要进行一系列操作，封装完成后进行成品测试，通常经过入检Incoming、测试Test和包装Packing等",
"level": 4,
"desc": null,
"alterName": null,
"chineseSemanticRule": [
"传统|芯片|封装",
"传统|微电路|封装"
],
"englisSemanticRule": null,
"englishSemanticRule": [
"Traditional|Chip|Package",
"Traditional|Microcircuit|Package"
],
"keywordExclude": null,
"knowledgeBottleneck": null,
"teckParam": null,
"version": 1.6,
"changedStatus": 0,
"mergedStatus": 0,
"isHooked": 0,
"children": [
{
"nodeId": "365316cf6f56f869c46701c4b581e9c9",
"parentId": "2d8f3327fd91a62cf6f13591b6930633",
"nodeCount": null,
"name": "SIP封装",
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}修改于 2023-05-25 03:14:02